1. Field of the Invention
The present invention relates to a semiconductor device, a method of manufacturing the same, and a silane coupling agent.
2. Description of the Related Art
In a structure proposed for a semiconductor device such as a NAND flash memory, although external dimensions are the same as those in the past, a storage capacity larger than that in the past is provided by laminating a plurality of memory chips on a wiring substrate stepwise and sealing the memory chips with resin (see, for example, Japanese Patent Application Laid-Open No. 2005-302871). To further increase the storage capacity in such a semiconductor device, it is necessary to increase the number of lamination steps of the memory chips. However, because there is a limit in the external dimensions, in particular, thickness of the semiconductor device, the thickness of the memory chips has to be reduced. Therefore, in recent years, thin-layering of semiconductor chips such as memory chips is advanced and the thickness of a wafer is reduced to be smaller than 100 micrometers. Usually, on the rear surface of the wafer, a fractured layer having unevenness is formed to suppress diffusion of ionic impurities from the rear surface to the inside of the wafer in a manufacturing process for a semiconductor device. However, when the thickness of the wafer is smaller than 100 micrometers, a deficiency tends to occur in that deflective strength of the chips falls and the chips are broken by pressure in mounting the chips. Therefore, the rear surface of the wafer (the chips) is planarized by polishing processing such as the chemical mechanical polishing (CMP) method or the etching method (see, for example, Japanese Patent Application Laid-Open No. 2007-48958).
However, when the rear surface of the wafer (the chips) is planarized by the polishing processing, the ionic impurities diffuse from the rear surface to the inside of the wafer as explained above. To cope with the problem, Japanese Patent Application Laid-Open No. 2007-48958 discloses that the fractured layer is left on the rear surface even in the case of the wafer having thickness smaller than 100 micrometers. However, in this case, the deflective strength of the wafer (the chips) falls because of the presence of the fractured layer. When the thickness of the wafer is smaller than 100 micrometers in this way, it is difficult to simultaneously attain the suppression of the diffusion of the ionic impurities to the inside of the wafer and the suppression of the fall in the deflective strength with the method in the past.